Accurate small signal modeling and extraction of silicon MOSFET for RF IC application

摘要

A simple scalable non-quasi-static (NQS) small signal equivalent circuit (SSEC) model of Si MOSFET and corresponding direct extraction methodology are developed in this paper. Compared with the conventional SSEC, a parallel gate drain branch is supplemented to describe parasitic gate-drain coupling under high frequency up to 40 GHz together with the impact of substrate loss, terminal resistances and inductances. The new extraction methodology is developed that all extrinsic parasitic components are extracted from zero bias Z-parameters and intrinsic components are extracted from ON state Y-parameters. The proposed model and extraction methodology are verified to achieve good agreement between simulated and measured S-parameters from 0.1 to 40 GHz for devices fabricated with 0.13 μm CMOS technology. The extracted bias dependent model could be further used to construct a nonlinear model in large signal applications.