机译:电路辅助方法对6T SRAM中余量和性能的影响
Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA;
rnDepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA;
rnDepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA;
rnDepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA;
rnIBM Microelectronics, Essex Junction, VT 05452, USA;
rnIBM Microelectronics, Essex Junction, VT 05452, USA;
rnDepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA;
SRAM; SNM; write margin; read assist; write assist; vmin; scaling; process variation; yield;
机译:紧凑型低VDDmin 6T SRAM,采用双分裂控制辅助方案,提高了单元稳定性,读取速度和写入余量
机译:单端28-NM CMOS 6T SRAM设计,具有读取辅助路径和PDP还原电路
机译:基于14μnmFinFET的6T SRAM单元功能的性能评估,用于直流和瞬态电路分析
机译:对6T SRAM单元设计中的性能和裕度读/写辅助技术的比较分析
机译:基于7NM FinFET的6T SRAM细胞瞬态和DC分析性能分析
机译:保证金评估方法对正保证金率和总交易量的影响
机译:用于低功耗的恢复电路减少6T和8T SRAM单元的摆动,改进了读写边距