机译:考虑栅极感应的漏极泄漏(GIDL)的低待机功耗(LSTP)操作的32 nm技术节点上的SOI FinFET设计
Inter-university Semiconductor Research Center (1SRC) and School of Electrical Engineering and Computer Science. Seoul National University, San 56-1. Sillim-dong. Cwanak-gu, Seoul 151-742, Republic of Korea;
Inter-university Semiconductor Research Center (1SRC) and School of Electrical Engineering and Computer Science. Seoul National University, San 56-1. Sillim-dong. Cwanak-gu, Seoul 151-742, Republic of Korea;
Nanoelectronks Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan;
Nanoelectronks Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan;
Nanoelectronks Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki, Japan;
Inter-university Semiconductor Research Center (1SRC) and School of Electrical Engineering and Computer Science. Seoul National University, San 56-1. Sillim-dong. Cwanak-gu, Seoul 151-742, Republic of Korea;
gate-induced drain leakage (CIDL); low standby power (LSTP); doping profile; numerical simulation; GIDL extraction;
机译:控制20nm级四端绝缘体上硅鳍形场效应晶体管的低待机功率操作,通过控制栅极下重叠长度来最小化栅极感应的漏漏
机译:使用栅极感应漏漏(GIDL)电流的无电容器1T-DRAM技术,用于低功耗和高速嵌入式存储器
机译:统一RAM(URAM)中无软编程操作的栅极感应漏泄(GIDL)编程方法
机译:考虑栅极感应的漏极泄漏(GIDL)的低待机功耗(LSTP)操作的32 nm技术节点上的SOI FinFET设计
机译:采用7NM FinFET技术的SRAM单元的漏电攻击恢复设计
机译:用于汽车压力和温度复合传感器的信号调理IC中采用180 Nm CMOS技术的低功耗小面积符合AEC-Q100标准的SENT发送器的设计
机译:通过优化22 nm和32 nm sOI nFET中的结型线来抑制栅极引起的漏极泄漏