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Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

机译:针对低能电路应用的交叉电流四极SOI MOSFET的初步器件模型和缩放方案的建议

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摘要

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I-V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.
机译:本文介绍了针对低功耗电路应用的交叉电流四极(XCT)绝缘体上硅(SOI)MOSFET的半分析模型和缩放方案的初步尝试。 XCT MOSFET的沟道电流模型分为本征MOSFET部分和寄生结栅场效应晶体管(JFET)部分。通过考虑MOSFET和JFET之间的电势耦合,提出了MOSFET和JFET的模型。本文的后面部分介绍了在原始SOI nMOSFET和XCT nMOSFET上的实验。本文着重介绍XCT器件结构的基本操作和特性。将半分析模型的I-V特性的计算结果与测量值进行比较。结果表明,所提出的模型成功地再现了测量值。此外,从针对低能耗电路应用的性能控制的角度讨论了XCT器件的设计指南和缩放问题。最后,揭示了XCT CMOS器件的初步电路仿真结果,以证明具有确定的低能耗性能。

著录项

  • 来源
    《Solid-State Electronics》 |2011年第1期|p.18-27|共10页
  • 作者单位

    ORDIST, Grad. School of Sci. and Eng.. Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan;

    rnORDIST, Grad. School of Sci. and Eng.. Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan;

    rnORDIST, Grad. School of Sci. and Eng.. Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan;

    rnORDIST, Grad. School of Sci. and Eng.. Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan;

    rnORDIST, Grad. School of Sci. and Eng.. Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    SOI MOSFET; Parasitic JFET; Differential negative conductance; Modeling; Performance control; Scaling scheme;

    机译:SOI MOSFET;寄生JFET;差分负电导;造型;绩效控制;缩放方案;

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