A mechanism for asymmetric data writing failure

摘要

As dynamic random access memory (DRAM) technology develops further, it is more difficult to sustain a sufficient sensing margin to detect weak cell data. Therefore, a high data writing performance is necessary in order to guarantee the data sensing margin. In this paper, an analysis of the phenomenon of an asymmetric data writing failure (ADWF) is presented, taking account of a bit line sense amplifier (BLSA) offset, and the failure mechanism has been studied through the use of measurement analysis.