On the effect of technology scaling on variation-resilient sub-threshold circuits

摘要

This paper studies the impact that CMOS technology scaling has on circuits operating in the ultra-low-voltage region. Sub-threshold circuits are an attractive option for energy-constrained applications, but the influence of scaling on the energy consumption has not been studied thoroughly on on-chip ultra-low-voltage implementations. This paper aims to provide an answer to the benefits and disadvantages of scaling on such implementations. First, an equation to determine the minimum feasible supply voltage for digital circuits is derived. Out of this equation, a theoretical minimum as well as a practical minimum supply for a specific technology can be calculated. Second, a 16-bit Multiply-Accumulate Unit is selected as a test vehicle to study scaling effects. This test vehicle is designed, processed and fully measured in both a 90 nm and a 40 nm CMOS technology. An extensive comparison between the measurement results of both designs allows to clearly examine the different technology scaling trade-offs.