机译:截止应力老化的p型多晶硅薄膜晶体管的栅诱导漏极泄漏电流特性
Sungkyunkwan Univ, Sch Elect Elect Engn, Coll Informat & Commun Engn, 300 Cheoncheon Dong, Suwon 440746, South Korea;
Sungkyunkwan Univ, Sch Elect Elect Engn, Coll Informat & Commun Engn, 300 Cheoncheon Dong, Suwon 440746, South Korea;
Sungkyunkwan Univ, Sch Elect Elect Engn, Coll Informat & Commun Engn, 300 Cheoncheon Dong, Suwon 440746, South Korea;
Korea Aerosp Univ, Sch Elect & Informat Engn, Goyang City 412791, Gyeonggi Do, South Korea;
Sungkyunkwan Univ, Sch Elect Elect Engn, Coll Informat & Commun Engn, 300 Cheoncheon Dong, Suwon 440746, South Korea;
Gate-induced drain leakage; Off-state stress; Charge trapping; Defect creation; Polycrystalline silicon thin-film transistor;
机译:多晶硅薄膜晶体管栅致漏漏电流的研究及其对漏极偏置扫描的抑制
机译:关态偏置应力下短沟道(L =1.5μm)p型多晶硅薄膜晶体管的阈值电压正移
机译:低温n沟道多晶硅薄膜晶体管在开态和关态应力下的应力感应截止电流
机译:通过漏极偏置扫描降低多晶硅薄膜晶体管的栅极感应漏极泄漏电流
机译:薄膜晶体管应用的多晶硅/电介质/衬底材料系统:材料特性对晶体管性能和可靠性的影响。
机译:A-Ingazno薄膜晶体管中光漏电流和负偏压照明应力的退火诱导稳定性的定量分析
机译:用鸟喙结构减少多晶硅薄膜晶体管漏电流的研究