Pragmatic Z~2-FET compact model including DC and 1T-DRAM memory operation

摘要

Z(2)-FET, a partially gated diode, was explored for Electrostatic Discharge (ESD) protection. Its sharp switching behavior is also promising for single-transistor (1T-DRAM) memory application. Based on detailed TCAD simulations, we develop a pragmatic SPICE compact model, including DC and memory operation. The model is validated via TCAD and experimental data. The proposed model reproduces the S-shaped V-I characteristics, the hysteresis and the turn on/off voltages. This model is implemented using Verilog-A and allows to evaluate, through SPICE simulation, the figures of merit for DC, transient and memory operation. It is useful for cell optimization and memory matrix design.