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In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors

机译:多晶硅垂直薄膜晶体管电气特性的深度分析

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摘要

A polycrystalline silicon vertical thin film transistor (VTFT) is fabricated, and the electrical parameters are extracted and compared with the typical lateral thin film transistor (LTFT). The similar subthreshold slope and the distinct field effect mobility is verified by the DOS calculation in the deep and shallow trap regions, respectively, and in this article, it is used to compare with the grain boundary trap density at a lower Vds = 10 mV that eliminates the velocity saturation effect. The accurate threshold voltage is also calculated by a systematic model including the grain boundary barrier modulation effect. A pseudo-subthreshold region is demonstrated, and the threshold voltage exactly corresponds to the 3kT point of the grain boundary barrier. The low field effect mobility of VTFT is mainly due to the small grain size and also slightly affected by the parasitic resistance, which can be improved by optimizing the processing conditions, especially by improving the sidewalls smoothness and the active layer quality.
机译:制造多晶硅垂直薄膜晶体管(VTFT),并将电参数与典型的横向薄膜晶体管(LTFT)进行比较。通过浅陷阱区域的DOS计算和在本文中,验证了类似的亚阈值斜率和不同的场效期移动性,它用于与较低VDS = 10 mV的晶界陷阱密度进行比较消除了速度饱和效应。精确的阈值电压也通过包括晶界屏障调制效果的系统模型来计算。对伪亚阈值区域进行说明,并且阈值电压与晶界屏障的3KT点完全对应。 VTFT的低场效果迁移率主要是由于小粒度小,并且也可以通过优化加工条件来改善寄生电阻略微影响,尤其是通过改善侧壁平滑度和有源层质量。

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