Optimization of deep well gate-controlled dual direction SCR device for ESD protection in 0.5 μm CMOS process

摘要

Both traditional dual direction SCR (TDDSCR) and deep well gate-controlled dual direction SCR (DGC-DDSCR) are designed and fabricated in a 0.5 mu m CMOS process. The ESD performance of the DDSCR device is predicted and verified by two-dimensional device simulation and transmission line pulse test results. The results show that when the TDDSCR changes the distance between the electrode N+ and the trigger surface P + (D4), the holding voltage increased from 10.1 V to 13.53 V, and the failure current remains stable (13.9A). The RS485 bus requires that the trigger voltage and the holding voltage of the ESD device be greater than 14.4 V, while TDDSCR is still unable to meet the on-chip ESD protection requirements for RS485 bus. However, when DGC-DDSCR increases the gate length (D4) of the anode and cathode, the holding voltage increases from 10.21 V to 15.18 V, and the failure current remains 14.63A. The test data has met the on-chip ESD protection requirements of the RS485 bus, and the size optimization problem of the DGC-DDSCR is discussed. The device has a strong current handling capability (91.25 mA/mu m).