CMOS high-speed dual-modulus frequency divider for RF frequency synthesis

摘要

The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presented. Compared to other designs fabricated with comparable CMOS technologies, this architecture has a better potential for high-speed operation. The circuit consumes less power than previously reported CMOS circuits, and it approaches the performance previously achieved only by bipolar or GaAs devices. The proposed circuit uses level-triggered differential logic to create an input-frequency-entrained oscillator performing a dual-modulus frequency division. In addition to high-speed and low-power consumption, the divider has a low-input signal level requirement which facilitates its incorporation into RF applications. Fabricated with a 1.2-/spl mu/m 5-V CMOS technology, the divider operates up to 1.5 GHz, consuming 13.15 mW, and requiring less than 100 mV rms input amplitude.