A 1-Gb SDRAM with ground-level precharged bit line and nonboosted2.1-V word line

摘要

This paper describes the key technologies used in a 1-Gbnsynchronous DRAM. This DRAM was developed according to a newncell-operating concept in which a ground-level (Vss)nprecharged bit line with a negative word-line reset scheme enables annonboosted 2.1-V word-line architecture. Total power consumption is lessnthan that of the conventional half-Vcc precharged bit-linenscheme. We also propose a vernier-type, high-accuracy delay-locked-loopncircuit realizing ±20-ps quantization errors for clock recoverynand skew elimination