A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bitsat Nyquist

摘要

A CMOS subranging analog-to-digital converter (ADC) incorporatesnseveral features to enhance performance and reduce power dissipation.nThe combination of an extended settling period for the fine references,nabsolute-value signal processing, and interpolation in the comparatornbanks alleviates the principal speed-limiting operation. A front-endnsample-and-hold amplifier (SHA) provides sustained dynamic performancenat high input frequencies and performs single-ended to differentialnconversion with a signal gain of two and with low distortion. The SHAnholds its differential output for a full clock cycle while itnsimultaneously samples the next single-ended input, thereby allowing itnto drive two comparator banks on consecutive clock phases. The remainingnanalog circuits are implemented in a fully differential manner. The usenof pipelining allows every input sample to be processed by the samenchannel, thereby avoiding the use of ping-pong techniques, whilenproviding a conversion latency of only two clock cycles. The dynamicnperformance with a single-ended input approaches that of an idealnill-bit ADC, typically providing 9.7 effective bits for low inputnfrequencies and 9.5 bits at Nyquist. This performance level isncomparable to the best reported for 10-bit CMOS ADC's with differentialninputs and significantly better than those with single-ended inputs. Thentypical maximum differential nonlinearity is ±0.4 LSB, and thenmaximum integral nonlinearity is ±0.55 LSB without trimming orncalibration. With an ADC power of 55 mW plus an SHA power of 20 mW fromna 5-V supply, the active area is 1.6 mm2 in a 0.5-Μmndouble-poly, double-metal CMOS technology