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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A microprocessor with a 128-bit CPU, ten floating-point MAC's, fourfloating-point dividers, and an MPEG-2 decoder
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A microprocessor with a 128-bit CPU, ten floating-point MAC's, fourfloating-point dividers, and an MPEG-2 decoder

机译:具有128位CPU,十个浮点MAC,四个浮点除法器和MPEG-2解码器的微处理器

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摘要

A 250-MHz microprocessor intended for home computer entertainmentnconsists of a CPU core with 128-b multimedia extensions, twonsingle-instruction, multiple-data (SIMD) very long instruction wordn(VLIW) vector processors containing ten floating-point multipliernaccelerators and four floating-point dividers, an MPEG-2 decoder, anten-channel direct memory access (DMA) controller, and other peripheralsnwith 128 b internal buses on one die. The core is a two-way superscalarnMIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vectornprocessor is a five-way SIMD-VLIW architecture, which is tightlyndedicated for specific applications concerning three-dimensionalngeometry calculation and physical simulation. A DMA controller connectsnbetween main memory and each processor's local memory to conceal memorynaccess penalty. It contains 10.5 M transistors in 17×14.1 mm andndissipates 15 W at 1.8 V
机译:一个用于家庭计算机娱乐的250 MHz微处理器,包括一个CPU核心,具有128-b多媒体扩展,两个单指令多数据(SIMD)超长指令字(VLIW)矢量处理器,其中包含十个浮点乘法加速器和四个浮点加速器。点分频器,MPEG-2解码器,十通道直接存储器访问(DMA)控制器和其他外围设备,在一个芯片上具有128 b内部总线。内核是具有16kB暂存RAM的双向兼容SuperscalarnMIPS的微处理器。每个矢量处理器都是五向SIMD-VLIW架构,对于涉及三维几何计算和物理模拟的特定应用,该架构是严格专用的。 DMA控制器连接主存储器和每个处理器的本地存储器之间,以隐藏​​存储器的访问开销。它包含17×14.1毫米的1050万个晶体管,在1.8 V时可吸收15 W功率

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