A 660-ΜW 50-Mops 1-V DSP for a hearing aid chip set

摘要

This article presents the flow and techniques used to design anlow-power digital signal processor chip used in a hearing aid systemnimplementing multiband compression in 20 bands, pattern recognition,nadaptive filtering, and finescale noise cancellation. The pad limited 20nmm2 chip contains 1.3 M transistors and operates at 2.5 MHznunder 1.05-V supply voltage. Under these conditions, the DSP consumesn660 ΜW and performs 50 million 22-bit operations per second,ntherefore achieving 0.013 mW/Mops (milli-watts per million operations),nwhich is a factor of seven better than prior results achieved in thisnfield. The chip has been manufactured using a 0.25-Μm 5-metal 1-polynprocess with normal threshold voltages. This low-powernapplication-specific integrated circuit (ASIC) relies on an automatednalgorithm to silicon flow, low-voltage operation, massive clock gating,nLP/LV libraries, and low-power-oriented architectural choices