A 4.5-mW 900-MHz CMOS receiver for wireless paging

摘要

An ultralow-power 900-MHz receiver implemented on a single CMOSnchip is intended for use in FLEX wireless paging. The receiver uses annindirect conversion to zero intermediate frequency (IF) to suppress thenflicker noise corner in the second mixer to less than 1 kHz. Variousntechniques for low-power design, most of them unique to CMOS, arenpresented, with theoretical support and experimental verifications. Thenreceiver, fabricated in a 0.25-Μm standard CMOS process, achievesn7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. Thenvoltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz atn25 kHz offset. The nominal receiver bias current of 3 mA is higher thannthe expected 2 mA because of unanticipated losses in coupling capacitors