Design of high-performance CMOS priority encoders andincrementer/decrementers using multilevel lookahead and multilevelfolding techniques

摘要

Lookahead signals to form the multilevel folding architecture fornpriority-encoding-based designs was used to improve the performance tonthe order of O(log N). Analysis showed that both the multilevelnlookahead and the multilevel folding techniques could be easily mergednand implemented in the dynamic CMOS circuits. For the 256-bit prioritynencoder, the new design adopting all the proposed techniques can achievennearly ten times performance while spending nearly half the powernconsumption as compared to the conventional design, utilizing only ansimple lookahead structure. For the 64-bit incrementer/decrementer, thennew design adopting all the proposed techniques requires less thannone-third delay time as compared to a high-speed carry-select addern(CSA)-based incrementer/decrementer. The power consumption evaluated atnthe maximum operating frequency and the transistor count of the newnincrementer/decrementer are also reduced to 67% and 35%, respectively,nas compared to the CSA-based design. The measurement results indicatenthat the proposed 256-bit priority encoder and the proposed 64-bitnincrementer/decrementer can operate up to 116 and 139 MHz, respectively,nwhen they are designed based on a 0.6-Μm CMOS technology