A Cost-Efficient High-Speed 12-bit Pipeline ADC in 0.18-μm Digital CMOS

摘要

A 12-bit pipeline ADC fabricated in a 0.18-μm pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2V{sub}(p-p) signal swing is applied. The occupied silicon area is 0.86 mm{sup}2 and the power consumption equals 97 mW. A switched capacitor bias current generator scales the opamp bias currents automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.