A Single-Chip UHF RFID Reader in 0.18 $mu{hbox {m}}$ CMOS Process

摘要

A single-chip UHF RFID reader that integrates all building blocks—including an RF transceiver, IQ data converters, and a digital baseband—is implemented in a 0.18 $mu{hbox {m}}$ CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag''''s response of $-$70 dBm in the presence of $-$5 dBm self-interferer while occupying 18.3 ${hbox {mm}}^{2}$.