A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations

摘要

This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When $N$ bit lines recycle their charges, the swing voltage and power of bit lines are reduced to $1/ N$ and $1/ N ^{2}$, respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K$,times,$ 8 bits is implemented in a 0.13-$mu{hbox {m}}$ CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at $ f _{rm CLK} =~{hbox {100 MHz}}$ and ${rm V} _{rm DD} =~hbox{1.2 V}$ .