Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability

摘要

A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was -112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was -104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30 MHz was 710 fs, and the corresponding reference spur level was -61.6 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm(2). Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply.