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An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing

机译:正交电流复用放大器,用于多通道感测

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We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channel's differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2$^{n}$) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 μV $_{rms}$ and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifier's four channels yields an effective NEF of 1.64. The total power consumption is 15.6 μW, or 3.9 μW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm$^{2}$ . The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers.
机译:我们演示了一种微功耗低噪声CMOS放大器阵列,该阵列可重复利用偏置电流来改善全差分放大器设计的基本噪声-功率折衷。所展示的电路通过堆叠四个放大器的差分输入对实现电流重用。每个通道的差分对的输出漏极电流都用作后续通道的差分对的尾电流。正交电流复用通过共享偏置器件来节省裕量,从而改善了噪声和功率折衷。从四个通道(n = 4)开始,有16个唯一的输出电流(2 $ ^ {n} $ )堆栈,每个堆栈都是四个输入的线性组合。通过在工作在低得多的偏置电流的输出级中适当组合小信号输出电流,可以重建原始输入信号的放大版本。输入参考噪声为3.7μV。噪声效率系数(NEF)为3.0。摊分放大器四个通道上的偏置电流可产生1.64的有效NEF。 1.5 V电源的总功耗为15.6μW,或每条路径3.9μW。正交偏置抑制了通道之间的串扰,在3-σ不匹配下提供了40 dB的隔离度。所实现的电路是用标准的130 nm CMOS工艺制造的,占用的面积为0.125 mm <公式> =“ inline“> $ ^ {2} $ 。所提出的技术对于从低功率神经记录阵列到多相无线电基带放大器的各种应用都是有用的。

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