Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier

摘要

An antenna load impedance detection and automatic tuning technique is presented. An antenna load impedance detection circuit as well as burst detector enabling autonomous tuning is integrated on a CMOS-PA chip. A low-loss impedance tuner with an SOI switch is also demonstrated. The proposed impedance detection circuit employs polar detection technique, so that the antenna impedance is tuned in a vector fashion to track the time-varying antenna impedance promptly. Also, it can operate with nonconstant envelope signal thanks to an introduced relative detection technique. At the back-off operation, the impedance can be automatically tuned to optimum value. The circuit is time shared with PA linearization loop, minimizing the overhead of the circuit. When the VSWR is approximately 2.5, the peak PAE is kept more than 40% with tuning, whereas it varies from 28% to 45% without tuning. The linear efficiency without the tuning is 15% as the worst case, while more than 30% of PAE is maintained when the tuning and PA-closed loop are enabled. The drain efficiency at 6 dB back-off is improved from 30% to 40%. The tuner can cover a VSWR of around 6, while achieving a loss ranging from 0.3 to 4.6 dB.