A 100–800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving $<-$40 dBc for ALL Harmonics

摘要

Radio transceivers capable of dynamic spectrum access require frequency-agile transmitters with a clean output spectrum. High- $Q$ filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional harmonic rejection mixers suppress only a few harmonics. This paper presents an 8-path polyphase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below $-$40 dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1 dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over three octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared with 50% improves power upconverter efficiency. A transmitter realized in 0.16- $muhbox{m}$ CMOS works from 100 to 800 MHz at a maximum single-tone output power of 10.8 dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is $>$21 dBm, while the LO leakage and image rejection is better than $-$ 45 dBc.