机译:具有功率和面积效率的10×10 Gb / s自举收发器,采用40 nm CMOS封装,可实现无参考和独立于通道的操作
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea;
Clocks; Voltage-controlled oscillators; Frequency locked loops; Transceivers; Phase noise; Jitter; Detectors;
机译:
机译:3.125至-28.125 GB / S 4.72 MW / GB / S多标准并行收发器支持40nm CMOS的通道无关操作
机译:具有直接调制数字发射器和I / Q相位耦合频率合成器的节能10-GB / S CMOS毫米波收发器
机译:具有功耗和面积效率的10×10 Gb / s自举收发器,采用40 nm CMOS,可实现无参考和与通道无关的操作
机译:用于串行10 Gb /秒数据传输系统的CMOS中新颖的模拟判决反馈均衡器。
机译:使用带有片上工作电极的10×10 CMOS IC电位阵列从硫蛋白细胞中释放神经递质的并联记录
机译:采用90nm CmOs的高功效2Gb / s收发器,用于10mm片上互连