High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic

摘要

A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 mu m*2.4 mu m and a maximum f/sub t/ of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees.