Formal verification and validation of embedded systems: the UML-based MADES approach

摘要

Formal verification and validation activities from the early development phases can foster system consistency, correctness, and integrity, but they are often hard to carry out as most designers do not have the necessary background. To address this difficulty, a possible approach is to allow engineers to continue using familiar notations and tools, while verification and validation are performed on demand, automatically, and transparently. In this paper we describe how the problem of making formal verification and validation tasks more designer-friendly is tackled by the MADES approach. Our solution is based on a tool chain that is built atop mature, popular, and widespread technologies. The paper focuses on the verification and closed-loop simulation (validation) aspects of the approach and shows how it can be applied to significant embedded software systems.