Yield Management: Reliability: The Big Hurdle in High-k Gate Dielectrics

摘要

Though high-k gate dielectrics demonstrate some of the same breakdown behavior as SiO_2-based dielectrics, certain mechanisms, such as charge trapping, occur much more readily in high-k devices. When a fixed charge density forms at the polysilicon/high-k interfaces, it typically accelerates negative bias temperature instability (NBTI) degradation and often leads to shifts in threshold voltage and flatband voltage. Much of the focus of current work is on testing high-k/poly and high-k/metal gate structures (see "How to Electrically Qualify High-k Gates," Semiconductor International, October 2003, p.51). There is also much research designed to understand the breakdown behavior and the causes of well-known phenomena of mobility degradation and Fermi-level pinning associated with high-k dielectrics.