Intel Takes 45 nm High-k/Metal Gate Process to IEDM

摘要

Intel Corp. (Santa Clara, Calif.) provided some details of its 45 nm high-k/metal gate process flow at the International Electron Devices Meeting (IEDM) in Washington, D.C., although key elements of the pFET electrode metal remained shrouded. Kaizad Mistry, vice president of logic integration, said Intel used a "high-k-first, metal gate-last" approach. By keeping the high-temperature annealing steps used to activate the dopants in between the dielectric and metal gate deposition steps, Intel is able to maintain a good workfunction metric for the electrode of its pFET transistor, which he said was 51% faster than the previous generation.