In-Die vs. Scribe-Line Copper CMP Monitoring

摘要

To minimize resistance-capacitance (RC) delays, logic device manufacturers have transi-tioned from aluminum to copper interconnects and oxide to low-k materials. Copper has reduced RC delays, electromigration problems and manufacturing costs. Until recently, however, aluminum has remained the metal of choice for most memory applications because memory devices generally require fewer levels of interconnect and operate at slower speeds than logic devices. At 45 nm and beyond, however, memory manufacturers are adopting copper interconnects for reduced manufacturing costs and increased yields. The copper damascene process is one in which in-die measurements can be critical in resolving the cause of yield excursions. Pattern-dependent electroplating effects have been extensively studied and are well understood. During electroplating, excessive copper buildup can occur on submicron line arrays, resulting in super-filled structures.