Metoda autonomicznej korekcji b??du nieliniowo?ci przetwornika czas-cyfra opartego na ró?nicowej linii opó?niaj?cej

摘要

The paper presents a new autonomous nonlinearity error correction method for vernier delay line (VDL, Fig. 1) based time-to-digital converter (TDC). The described VDL consists of flip-flops and two delay chains. The first chain is composed of voltage controlled delay buffers (Fig. 3a) and the second one utilizes digitally controlled shunt capacitor scheme (Fig. 3b). In order to accomplish nonlinearity correction both delay chains in VDL are first set to the same delay using voltage controlled buffers, then the delays of buffers in both chains are compared with use of flip-flops and adjusted with shunt capacitor controlled buffers. Finally, once more the voltage controlled buffers are used to increase VDL delay and achieve the needed LSB. The simulations show that nonlinearity error reduction by an order of magnitude is possible with this method. Monte Carlo simulations performed with 16 stages VDL (CMOS 0.35 μm) indicate that integral nonlinearity (INL) error can be less than 1 ps (Fig. 4b). Some predictions about max INL error based on time model are also presented. Moreover, nonmonotonic VDL can also be corrected, which improves attainable resolution. In opposition to the previously proposed VDL calibration methods[l, 3, 4, 5, 6], there is no need for either implementing accurate signal sources or generating a large number of uncorrelated time events like in the code density method.%W artykule zaprezentowano now? metod? autonomicznej uk?adowej korekcji b??du nieliniowo?ci przetwornika czas-cyfra opartego na noniu-szowej linii opó?niaj?cej. Wyniki symulacji pokaza?y, ?e mo?liwe jest zmniejszenie b??dów nieliniowo?ci o rz?d wielko?ci. W symulacji Monte Carlo dla szesnastokomórkowej linii noniuszowej zaprojektowanej w technologii CMOS 0.35 um i ?rednim opó?nieniu komórki wynosz?cym 10 ps, otrzymano b??dy nieliniowo?ci sumacyjnej INL mniejsze ni? 1 ps.