Sprz?towa implementacja algorytmu detekcji wzorców b??dów DCT w hybrydowym algorytmie maskowania b??dów transmisji obrazu sta?ego HECA

摘要

The paper presents a conception of hardware implementation of DCT pattern detection module of Hybrid Error Concealment Algorithm (HECA) [2]. The research is aimed at implementing a hardware version of the module, using possibilities of parallel operation in FPGA and optimizing the algorithm structure for hardware implementation and performance. Paragraph 1 gives introduction to digital image transmission error concealment. Paragraph 2 presents a structure and operation of the HECA algorithm. The dataflow is presented (Fig. 1.) and the implemented module is identified. Paragraph 3 deals with the mechanism of DCT error pattern occurring [3] and describes a method for detection of such patterns [2]. Paragraph 4 is focused on operation of the error pattern module of HECA in details. There are presented specific features of error patterns for a given DCT block size (Tab. 1) The erroneous block data example is shown in Fig. 2., while the error location storing example is presented in Fig. 3. The operation algorithm for error pattern detection is discussed and presented in Fig. 4. Paragraph 5 describes hardware implementation procedures. The implementation process is presented, the structure of hardware solution is shown (Figs. 5, 6, 7.) and discussed. The hardware resources consumption of the synthesis results is given in Tab. 2. Paragraph 6 contains the conclusion and directions for the future work. The research conclusions are that the DCT error pattern detection algorithm can be successfully implemented in FPGA with acceptable resources consumption. Such an implementation allows performing some of the algorithm elements in parallel, accelerating the operation. The problem is that the data amount tends to be high and it would be recommended to develop more effective notation to store such data in FPGA.%W artykule przedstawiono wyniki badań nad realizacj? sprz?tow? modu?u detekcji wzorców b??dów transmisji obrazu sta?ego. Jest on cz??ci? hybry dowego algorytmu maskowania b??dów transmisji HECA. Opisano pod stawy dzia?ania aparatu analitycznego, algorytm jego dzia?ania oraz reali zacj? sprz?tow? na poziomie behawioralnym. Wyró?niono najistotniejsze bloki implementacyjne, zaprezentowano wyniki syntezy w ?rodowisku Quartus II v.9.1 dla uk?adu FPGA klasy Stratix III EP3SL70 oraz przedys kutowano uzyskane wyniki.