RELIABILITY CHALLENGES FOR LOW VOLTAGE/LOW POWER INTEGRATED CIRCUITS

摘要

This review paper discusses reliability considerations for low voltage/low power integrated circuit technologies. This growing market will continue to be dominated by scaled CMOS, with silicon on insulator technology growing in importance due to improved performance and reliability over bulk, low power CMOS. Power dissipation, performance, and reliability will be traded off at all levels of system design; this paper concentrates on device level issues. An aggressive low voltage/low power technology development path could yield a CMOS/SOI technology with 40 nm junctions, 5 nm gate oxides, and 0.9 V supplies. Such an aggressive low voltage/low power technology alters many traditional reliability problems such as metallization failure, oxide breakdown, hot carrier effects, electrostatic discharge, leakage currents, soft errors and analogue circuit noise. SOI brings additional reliability concerns such as heat dissipation through the buried oxide, bipolar latch, and back interface effects. This paper examines several of these issues and identifies a number of present and future reliability challenges for low voltage/low power technology.