MODELLING AND ESTIMATION OF WAFER YIELDS AND DEFECT DENSITIES FROM MICROELECTRONICS TEST STRUCTURE DATA

摘要

Test structures are being used widely in microchip manufacturing in order to extract yield information for VLSI circuits manufactured in the same technology. We present and discuss a statistical method used for predicting full scale wafer yields, based on an 'outlier detection' principle applied to scaled test structure electrical and visual data. A case study, based on data from a joint ALCATEL ESPACE/INTELSAT research project, illustrates a successful application of this methodology.