Electrical characterization of trapping phenomena at SiO_2/SiC and SiO_2/GaN in MOS-based devices

摘要

In this paper, some aspects of the electrical characterization of trapping phenomena occurring at interfaces between insulators and wide band semiconductors (WBG) are presented, with a focus on the SiO_2/SiC and SiO_2/GaN systems. In particular, time resolved capacitance, current measurements, and parallel conductance measurements as a function of frequency were correlated to investigate trapping stales in SiC and GaN MOS-structures, allowing to distinguish between slow and fast states in these systems. Furthermore, gate current measurements enabled us to get insights into the near interlace traps (NITs) present inside the SiO_2 layer. Evidently, in these systems, although post-oxide deposition annealing treatments can reduce the interface traps (down to the 10~(11)-10~(12) cm~(-2) eV~(-1) range), the presence of the NITs is responsible for an anomalous behavior of the current conduction, penalizing the threshold voltage stability. Time-dependent current and conductance measurements, performed in appropriate bias ranges, enabled to determine the density of NITs (1 × 10~(11) cm~(-2)). The impact of the observed trapping phenomena on the SiO_2/SiC(GaN) transistor operation is briefly discussed.