The performance of the interprocessor communication architecture of the CM-2 is analyzed. A discrete-time Markov chain model of its network architecture is developed to compute the message delay introduced by the network architecture. Due to the synchronous time-division multiplexing nature of the network operation, it is amenable to a discrete-time Markov chain modeling. The analysis yields formulas for response time and several other related performance measures, showing how the performance of the network degrades with the message arrival rate and other parameters. Since the communication delays affect interprocess communication, knowledge of the sensitivity of the delays to the parameters can be a useful aid in designing a high performance parallel system. To keep the analysis tractable, an approximate Markov model is used that requires the use of fixed-point iteration for its solution. Validation of the results against a simulation study reveals that the analysis predicts the performance of the network with high accuracy.
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