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An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays

机译:具有可变树突延迟的新型一元尖峰神经网络乘法器的高效硬件实现

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摘要

We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the dendritic delays on customized neuromorphic hardware are the major contributions of this work. The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma. The multiplier eliminates complex rules by adopting the soma model with dendritic connectivity configurations, increasing the processing speed compared with previously reported solutions based on Spiking Neural Networks. (C) 2016 Elsevier B.V. All rights reserved.
机译:我们提出了一种新颖的一元加标电路,用于具有可变树突延迟的串行乘法器。串行乘法器通常使用体模型进行算术运算。串行乘法器的结构以及在定制的神经形态硬件上有效实施树突状延迟是这项工作的主要贡献。乘法器的设计灵感来自树突的生物过程,该过程使用反馈连接和树突生长来同步体细胞执行的神经处理。通过采用具有树突连通性配置的躯体模型,该乘数消除了复杂的规则,与先前报告的基于Spiking Neural Networks的解决方案相比,提高了处理速度。 (C)2016 Elsevier B.V.保留所有权利。

著录项

  • 来源
    《Neurocomputing》 |2016年第12期|130-134|共5页
  • 作者单位

    Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico;

    Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico;

    Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico;

    Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico;

    Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico|ESIME Culhuacan, Mexico City, DF, Mexico;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    FPGA; Unary multiplier; Dendritic delays; Neuromorphic;

    机译:FPGA;一元乘法器;树突延迟;神经形态;

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