Synthesis of Circuits Admitting Complete Checking Tests of Constant Length under Inverse Faults at Outputs of Elements

D. S. Romanov

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Synthesis of Circuits Admitting Complete Checking Tests of Constant Length under Inverse Faults at Outputs of Elements

机译：允许在元件输出出现反向故障时进行恒定长度的完整检查测试的电路综合

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摘要

A method for synthesizing circuits of functional elements in a special basis which admit complete checking tests of length at most 4 under inverse faults at the outputs of functional elements is proposed.

机译：提出了一种在特殊基础上合成功能元件电路的方法，该方法允许在功能元件的输出出现反向故障时对长度最多为4的完整检查测试。

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来源
《Moscow University Computational Mathematics and Cybernetics》 |2015年第1期|26-34|共9页
作者
D. S. Romanov;
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作者单位

Department of Computational Mathematics and Cybernetics, Moscow State University, Moscow, 119991 Russia;

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原文格式 PDF
正文语种 eng
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关键词
checking test; circuit of functional elements; inverse fault; Shannon function; easy-to-test circuit;

机译：检查测试;功能元件电路;反故障香农功能;易于测试的电路;

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专利

1. On the synthesis of circuits admitting complete fault detection test sets of constant length under arbitrary constant faults at the outputs of the gates [J] . D. S. ROMANOV Discrete mathematics and applications . 2013,第3a4期

机译：关于在门的输出端允许任意恒定故障下允许恒定长度的完整故障检测测试集的电路的综合
2. Method of synthesis of easily testable circuits admitting single fault detection tests of constant length [J] . Dmitry S. Romanov Discrete mathematics and applications . 2014,第4期

机译：易于测试的电路的合成方法，允许进行恒定长度的单个故障检测测试
3. Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements [J] . YU. V. BORODINA, P. A. BORODIN Discrete mathematics and applications . 2010,第4期

机译：在元件输出处出现类型0恒定故障的情况下，基于Zhegalkin的易于测试的电路的综合
4. Synthesis of multi-level combinational circuits for complete robust path delay fault testability [C] . Jha, N.H., Pomeranz, Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on . 1992

机译：综合多级组合电路以实现完整的鲁棒路径延迟故障可测试性
5. Hierarchical process variability analysis for analog circuits and its application to test development, fault diagnosis, yield estimation, and design synthesis [D] . Liu, Fang 2007

机译：模拟电路的分层过程可变性分析及其在测试开发，故障诊断，成品率估计和设计综合中的应用
6. Neural Circuits: Forward and inverse effects of the complete electrode model in neonatal EEG [O] . S. Pursiainen, S. Lew, C. H. Wolters -1

机译：神经回路：新生儿脑电图中完整电极模型的正向和反向作用
7. About the reliability of circuits with faults of type 0 at the outputs of elements in the complete finite basis containing a special function [O] . Marina Anatolevna Alekhina, Yulia Sergeevna Gusynina, Tatana Aleksandrovna Shornikova 2019

机译：关于在包含特殊功能的完整有限基础上的元素输出中与类型0的电路的可靠性
8. Checking Experiments for Output Faults. [R] . boute,raymond t. 1975

机译：检查输出故障的实验。

Synthesis of Circuits Admitting Complete Checking Tests of Constant Length under Inverse Faults at Outputs of Elements

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