A Low-Power 255-GHz Single-Stage Frequency Quadrupler in 130-nm SiGe BiCMOS

摘要

A frequency quadrupler for the up-conversion of a 63.75-GHz signal to an output frequency of 255 and 12.7 GHz of bandwidth for use in a local oscillator chain is presented. The presented circuit extends the common push-push architecture to a single-stage frequency quadrupler and improves upon existing designs concerning frequency of operation and conversion core efficiency. By replacing the usual 2 x 2 architectures with the presented solution, the total dc power consumption can be reduced by over 75% with respect to state-of-the-art designs, while maintaining useful output power levels. To showcase the performance of the core, the design abstains from any buffers at the input or output. Consuming 22.4 mW the circuit produces -8.4 dBm of output power. Excluding the losses in the passive input network, the circuit achieves a conversion loss of 4.4 dB. The fundamental suppression is higher than 40 dB.