Data communication management in system specification

摘要

In this paper, a powerful communication scheme is introduced to efficiently meet different communication requirements for behavioural synthesis from VHDL. The algorithmic description of the system behavivour is specified through a set of cooperating VHDL processes. Communication between processes is provided by the definition of a message-passing communication scheme, to efficiently manage both synchronised and unsynchronised data exchange. A way to effectively map message passing to shared memory for system synthesis is also presented. The proposed data communication scheme has been successfully tested with the VHDL model of the control of an ATM node.