Optimal processor dynamic-energy reduction for parallel workloads on heterogeneous multi-core architectures

摘要

With the increase in the number of cores in processor chips observed in recent years, design choices such as the number of cores in chip, the amount of resources per core, and whether to design homogeneous or heterogeneous chips need to be given proper support. Several studies on heterogeneous multi-core processors are concerned with performance improvements. In this work, we propose mathematical models to analyze some of these design issues with focus on the reduction of processor dynamic energ