VLSI architecture for Vasanth sorting to denoise image with minimum comparators

摘要

An efficient VLSI architecture for minimized sorting network (Vasanth sorting) in rank ordering application to remove salt and pepper noise is proposed. The basic operation in salt and pepper noise removal is rank ordering. In this work, a novel 2D sorting technique referred to as Vasanth sorting is proposed for a fixed 3 x 3 window. Vasanth sorting requires only 25 comparators to sort 9 elements of the window. A parallel architecture is developed for Vasanth sorting with 25 comparators. The processing element of the parallel architecture is an 8-bit data comparator (Two cell comparator). The performance of the proposed sorting technique is compared with the different sorting technique which is targeted for XCV1000-5bg560 on XILINX 7.1i and xc7v2000t-2fig1925 Xilinx 14.7 project manager respectively with Modelsim 10.4a for simulation and XST compiler tool for synthesis using VHDL. It was found that the parallel architecture developed for Vasanth sorting requires the only 1/4 of the area in FPGA when compared to existing sorting techniques. The combinational delay of the proposed architecture was also twice as less like their counterparts. The power consumption of the logic was 7mw. Hence the above performances make Vasanth sorting a better choice compared to existing techniques for rank ordering. (C) 2019 Elsevier B.V. All rights reserved.