A TDC-less all-digital phase locked loop for medical implant applications

摘要

A TDC-Iess, ultra-low area and low power all-digital phase locked loop (ADPLL) has been designed for use in biomedical implant transceivers. The proposed ADPLL eliminates the use of LC oscillator and time-to digital converter (TDC) for achieving a low power and low area implementation suitable for biomedical implants. Circuit design techniques such as capacitive boosting and fractional capacitor tuning have been applied to the ring oscillator of the proposed ADPLL for achieving good jitter performance. The ADPLL has been fabricated in 40 nm CMOS and occupies an active area of only 0.0186 mm(2). Measurement results demonstrates that the ADPLL can provide differential output signal with a frequency range from 330 MHz to 470 MHz while operating at a supply of 0.68 V. The ADPLL consumes a power of 248.62 mu W at 0.68V supply while running at an output frequency of 401 MHz and exhibits an rms jitter of 11.88 ps. The measured phase noise of the ADPLL is -98.76 dBc/Hz at 1-MHz frequency offset. The ADPLL's applicability in cochlear implant applications is also discussed. (C) 2019 Elsevier B.V. All rights reserved.