Evaluating the impact of reissued instructions on data speculative processor performance

摘要

In this paper, we investigate the impact of instructions reissued due to misspeculated data dependence on processor performance. Recently, the practice of speculation in resolving data dependences has been studied as a means of extracting more instruction level Parallelism. When a misspeculation occurs, it is necessary to revert the processor state to a safe point where the speculation is initiated, With an instruction reissue mechanism utilized for that purpose. The instruction reissue suffers less miss penalties than instruction squashing Which handles misspeculated control flows in current generation processors, but causes redundant instruction dispatching, i.e. multiple copies Of an instruction are in flight in functional units.