SAME TRANSISTORS,NEW NAMES: Foundries Rename Nodes to Disguise Lack of Progress

摘要

Intel's plan to stop using nanometers to identify its transistor nodes symbolizes the problem facing all leading-edge foundries. Despite the best efforts of process engineers, Moore's Law is hitting the proverbial wall. Accurate labels based on nanometers would clearly show the lack of progress in shrinking transistors. That leaves foundries with two choices: lie using nanometers, or lie without nanometers. For the last few generations, TSMC has chosen the former. Back in the day, we labeled IC processes using the contacted-gate pitch, which is the distance between closely packed transistors. Because this distance (measured in nanometers) is linear, die area scaled with the square of the pitch. To achieve the Moore-prescribed goal of doubling transistor density, the gate pitch dropped by about 30% in each node: for example, 40nm to 28nm.