Reduction of the parasitic charge generation during silicon nitride deposition deposition in a LOCOS isolation without field implant

摘要

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field impart) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and meal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.