The relentless march of the MOSFET gate oxide thickness to zero

摘要

The narrowest feature of integrated circuit is the silicon dioxide gate dielectric (3-5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may prelude the use of silicon dioxide as the gate dielectric for thickness less than 1.3 nm, however.