An efficient approach to the measurement and characterization of MOSFET capacitance

摘要

This article describes an improved methodology of estimation of the components of MOS tansistor gate capacitances. It uses transistors on a test structure, which was designed for the purpose of a general characterization of CMOS technology and devices. The presented method is based one comparison of the appropriate C-V characteristics of transistors of different gate dimensions. This allows efficient elimination of undesired parasitic capacitances of the measurement setup.