Full-Chip Reliability Simulation for VDSM Integrated Circuits

摘要

The most common circuit reliability concerns, the hot carrier degradation, the bias temperature instability and the electromigration failure, are discussed in this tutorial with emphasis on the full-chip design flow. Here the emphasis is on the design for reliability rather than the more popular TD fix of these issues. It has been shown that in the era of VDSM with more advanced processes such as SOI, thin dielectric film and copper interconnect, more degradation mechanisms need to be investigated and more complicated modeling issues need to be solved for accurate and efficient reliability simulation. Both full-chip transistor-level and cell based solutions should be provided for circuit designers with million-transistor/gate capacity and high accuracy. Reliability simulation constitutes one of the key roles in the silicon-accuracy sign-off flow for full-chip designs, as well as the parasitic extraction, coupling noise timing analysis and power grid IR drop analysis.