Ultra-Thinning of C4 Integrated Circuits for Backside Analysis during First Silicon Debug

摘要

We have developed a novel reliable technique to globally thin the backside of silicon die to 10μm with thickness control of l2μm and flatness variation of 2μm across 1cm × 1cm devices. This paper discusses this new technique to thin the silicon substrate of C4 package as well as various tests used to verify functionality. Functionality of thinned devices from three different manufacturers has been proven. Application of this method enhances the ability for optical navigation across a lcm x lcm die and the performance of non-contact probing such as LVP or PICA because of improved signal levels. In addition, sample preparation for FIB failure analysis and de-bug is greatly simplified. This technique can be used during first silicon debug, yield enhancement and failure analysis to assist the identification of fault sites.